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    • 专利摘要:
    The invention relates to a two-to-one logic multiplexer (7) comprising: two input terminals (A, B); an output terminal (Z); a control terminal (S); and a plurality of four one-to-one unit multiplexers (72, 74, 76, 78) connected in series, a first unitary multiplexer (72) having its inputs connected to the input terminals, a last unitary multiplexer (78) having its output connected to the output terminal and the other unitary multiplexers (74, 76) having their respective inputs interconnected to the output of the preceding multiplexer in the series association, one-half of the unit multiplexers being reverse-controlled (75) with respect to a other half.
    公开号:FR3051085A1
    申请号:FR1654080
    申请日:2016-05-04
    公开日:2017-11-10
    发明作者:Albert Martinez；Michel Agoyan
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    MULTIPLEXER STRUCTURE
    Field
    The present description generally relates to electronic circuits and, more particularly, to electronic circuits or functions that can be used as in an electronic circuit or device. An example of the application of the circuits and electronic functions of the present description is the realization of a random number generator. Another example of application is the realization of a non-clonable physical function (PUF), for example to generate unique identifiers or unique cryptographic keys. The present disclosure relates more particularly to random number generators in security applications such as encryption, authentication, etc.
    Statement of Prior Art
    In many applications, processing units, for example CPUs, microcontrollers, use randomly generated numbers.
    Random number generation circuits use various circuits or subsets that may have other applications out of the generation of random numbers. In particular, a random number generator uses oscillator, multiplexer and so on circuits. which, although particularly interesting in the generation of random numbers, are not limited to these applications.
    The number generators to which the present description applies are based on the use of delay lines looped over each other.
    There is a need for improvement of random number generators or circuits providing non-clonable physical functions.
    More generally, there is a need for improvement of logical electronic functions, usable not only in random or reproducible number generation applications, but also in other applications where similar problems arise. summary
    One embodiment overcomes all or part of the disadvantages of the usual solutions for generating random numbers or physical functions for unique identifiers, cryptographic keys, etc.
    An embodiment according to one aspect of the present description proposes a circuit whose behavior can be modeled to produce an oscillation number generator for generating random numbers or a non-clonable number.
    An embodiment according to this aspect proposes a generator whose behavior can be verified.
    An embodiment according to this aspect proposes a solution compatible with the use of standard cells of a given electronic technology.
    An embodiment according to another aspect of the present description proposes a symmetrical multiplexer structure, that is to say having a similar temporal behavior for passing a rising edge and for passing a falling edge.
    An embodiment according to this other aspect proposes a multiplexer structure compatible with the usual multiplexer structures.
    An embodiment according to yet another aspect of the present description proposes a counter of change of state (oscillations) of noisy signals.
    An embodiment according to this still another aspect provides a solution more particularly adapted to the counting of an output of an oscillation generator.
    Thus, an embodiment of a first aspect provides a circuit for generating a number of oscillations comprising: a first branch comprising at least one delay line providing symmetrical delays on rising edges and on falling fronts and at least one asymmetrical retarding element providing different delays on rising edges and on falling fronts; a second branch, looped back on the first and comprising at least one delay line providing symmetrical delays on rising edges and falling edge.
    According to an embodiment of this first aspect, the second branch further comprises at least one asymmetrical delay element providing different delays on rising edges and on falling edges.
    According to an embodiment of this first aspect, NAND gates, combining the respective outputs of the branches with a control signal, are interposed between the respective outputs of each branch and the input of the other branch.
    According to one embodiment of this first aspect, the delay lines consist of logic elements reducing to a non-inverting function at a single input and whose rise and fall times are identical.
    According to an embodiment of this first aspect, the one or more delaying elements consist of non-inverting logic circuits.
    According to an embodiment of this first aspect, each delay element consists of a logic function that can be reduced to a non-inverting function that depends only on a single input and whose rise and fall times are different. .
    According to an embodiment of this first aspect, the branch or branches also comprise a second delay line providing symmetrical delays on rising edges and on falling edges, connected in parallel to the delay element of the branch concerned.
    An embodiment also provides a number generator comprising: at least one generation circuit of a number of oscillations; and at least one counter of the number of oscillations generated by said circuit.
    According to one embodiment, said circuit is configured to generate a random number of oscillations.
    An embodiment also provides an electronic device having at least one number generator configured to generate a reproducible number.
    An embodiment of a second aspect provides a two-to-one logic multiplexer comprising: two input terminals; an output terminal; a control terminal; and a plurality of four serial multiplexers two to one connected in series, a first unitary multiplexer having its inputs connected to the input terminals, a last unitary multiplexer having its output connected to the output terminal and the other unitary multiplexers having their respective inputs interconnected at the output of the preceding multiplexer in the series association, one half of the unit multiplexers being controlled in inverse relation to another half.
    According to an embodiment of this second aspect, the unitary multiplexers are inverter multiplexers.
    According to an embodiment of this second aspect, all the unitary multiplexers are identical.
    According to an embodiment of this second aspect, one half of the multiplexers has its control inputs connected to said control terminal.
    According to an embodiment of this second aspect, the other half of the multiplexers has its control inputs connected to the output of a multiplexer whose input is connected to said control terminal.
    One embodiment also provides a four-to-one multiplexer having three two-to-one logic multiplexers.
    An embodiment also provides a number generation circuit, comprising at least one multiplexer as above.
    An embodiment of a third aspect provides a pulse counting circuit provided by a circuit having at least two inverted pulse signal supply terminals, comprising: a first pulse counter of a first pulse signal providing a first count ; a second pulse counter of a second pulse signal providing a second count; and a selection element of one of the accounts.
    According to an embodiment of this third aspect, the selection element receives, in addition to the counts provided by the counters, said pulse signals.
    According to an embodiment of this third aspect, the selection element takes into account the disappearance of pulses of one of the pulse signals.
    According to an embodiment of this third aspect, the selected count is that of the counter whose pulse signal stops first.
    According to an embodiment of this third aspect, the selected count is that of the counter whose pulse signal stops last.
    According to an embodiment of this third aspect, the account selected is that of: the counter having the largest account if the two accounts have the same parity; or the counter with the largest account if this account is even and the smallest if the account is odd.
    According to an embodiment of this third aspect, the selection circuit provides the least significant bit of the selected account.
    According to an embodiment of this third aspect, the pulses are provided by two delay lines looped over one another of an oscillation generator.
    According to an embodiment of this third aspect, the pulse counting circuit further comprises, upstream of each counter, a pulse shaping circuit.
    According to an embodiment of this third aspect, the shaping circuit comprises a flip-flop whose output is looped back to an initialization or reset input (RN) after passing through a delay element.
    According to an embodiment of this third aspect, the delay provided by the delay element is greater than the minimum duration of taking into account a pulse by the flip-flop.
    One embodiment provides a number generation circuit having at least one pulse counting circuit.
    Brief description of the drawings
    These and other features and advantages will be set forth in detail in the following description of particular embodiments made without implied limitation in relation to the appended figures, in which: FIG. 1 is a diagrammatic representation in the form of FIGS. blocks, an embodiment of an electronic circuit of the type to which the described embodiments apply; FIG. 2 represents an exemplary circuit for generating a number of oscillations for a random number generator or a non-clonable number generator; FIGS. 3A, 3B, 3C, 3D and 3E illustrate, in the form of chronograms, a new interpretation of the operation of a generator of a number of oscillations; FIG. 4 represents an embodiment of an oscillation generator; FIG. 5 schematically shows in the form of blocks an alternative embodiment of a generator of a number of oscillations; FIG. 6 schematically represents an embodiment of delay lines for oscillation number generator; FIG. 7 schematically represents an embodiment of a two-to-one symmetric multiplexer circuit; Fig. 8 shows an embodiment of a four-to-one symmetric multiplexer; Fig. 9 shows an embodiment of a random number generator based on a number of oscillations generator; FIG. 10 represents an embodiment of a circuit for shaping a pulse signal; and FIGS. 11A, 11B, 11C and 11D illustrate, in the form of timing diagrams, the operation of the shaping circuit of FIG.
    detailed description
    The same elements have been designated with the same references in the various figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and will be detailed. In particular, the uses of the numbers generated (random or nonclonable) and the applications of the circuits integrating the generator described have not been detailed, the embodiments described being compatible with the usual uses and applications. In an arbitrary manner, state 1 denotes the high state of a logic signal and state 0 its low state. When referring to the terms "about", "approximately" or "of the order of", this means to within 10%, preferably to within 5%.
    The number generator object of the present description is described later in connection with an example of a random number generator of oscillations. Unless otherwise specified, all that is described below, however, applies to a vibration number generator for non-clonable physical function.
    FIG. 1 very schematically represents an electronic circuit 1 of the type to which the embodiments which will be described will be applied.
    The circuit 1 comprises, inter alia: a computing entity 12 or processing entity (PU), for example a state machine, a microprocessor, a programmable logic circuit, etc. ; one or more zones 14 (MEM) of volatile and / or non-volatile storage for storing all or part of the data and keys; one or more circuits 16 implementing various functions (FCT) related to the application for which the circuit 1 is intended, for example a crypto processor, a control circuit of a biometric sensor, etc. ; one or more buses 17 of data, addresses and / or commands between the various elements internal to the circuit 1 and an input / output interface 19 (I / O) for communication with the outside of the circuit 1; and one or more random number generator circuits 2 (RNG).
    FIG. 2 represents an exemplary electrical diagram of a generator 10 that is usual for a number of oscillations for a random number generator.
    This generator 10 is based on two delay lines each composed of delay elements in series, looped back on one another, each delay element restoring the signal in the same state (1 or 0) as its input. The number of delay elements of each string may be different or the same. In the example shown, a first line 11 comprises four elements delay elements 111, 112, 113 and 114 in series between an output terminal 131 of a first logic gate 13 of the NAND type (NAND) and a first terminal. input 153 of a second logic gate 15 of the NAND type. A second line 17 has three delay elements 171, 172 and 173 in series between an output terminal 151 of the second door 15 and a first input 133 of the first door 13. The respective second inputs 135 and 155 of the logic gates 13 and 15 constitute input terminals intended to receive the same control signal CTRL (triggering the generation of a number). The number of oscillations, which conditions the random number, is taken, for example, at the output of the first line, that is to say on the first input 153 of the gate 15. In a variant, the number of oscillations is taken at the input 133 of the door 13, at the output 131 of the door 13 or at the output 151 of the door 15.
    The difference between the delays brought by the two lines conditions the duty cycle of the signals present at the terminals 133 and 153.
    In theory, the generator of FIG. 2 oscillates indefinitely with a duty cycle as long as the signal CTRL is in state 1. In practice, in the absence of noise but with delay elements (logic gates) having different times which eventually deform the duty cycle sufficiently for the oscillator to stop, the generator eventually stops after a fixed number of oscillations. In the presence of noise (jitter phase jitter), the generator ends up but stops after a number of oscillations whose value varies.
    Thus, the fact that the generator stops is not in itself annoying, quite the contrary, but what is annoying is not being able to determine around what value (what number of oscillations) it will stop. Indeed, for the random number generator to work properly, it must accumulate enough noise, so a sufficient number of oscillations so that the result of counting the number of oscillations provides, when the counter stops , a sufficient hazard at its least significant bit or a few (less than ten) least significant bits of the oscillation counter.
    The embodiments described below have their origin in a new analysis of the behavior of a generator of numbers of oscillations.
    In particular, the inventors have found that it is possible to link the behavior of the oscillation number generator with the intrinsic but quantifiable parameters of the elements that constitute it.
    FIGS. 3A, 3B, 3C, 3D and 3E illustrate, in chronograms, the theoretical operation of the circuit of FIG. 2. FIG. 3A represents an example of the appearance of the signal CTRL. FIG. 3B illustrates a corresponding example of the appearance of the signal present on the output 131 of the door 13. FIG. 3C illustrates a corresponding example of the appearance of the signal present on the output of the first line (the entry 133 of the door 13). FIG. 3D illustrates a corresponding example of the appearance of the signal present on the output 151 of the door 15. FIG. 3E illustrates a corresponding example of the appearance of the signal present on the output of the first line (the input 153 of the door 15).
    It is assumed that the delay provided by each door and by each delay element is equal to a value equal to all elements and doors.
    When the signal CTRL is in the 0 state, the outputs 131 and 151 are always in the state 1. Therefore the outputs 133 and 153 of the lines 17 and 11 are stable at the state 1. At a time t30 , the CTRL signal is switched to state 1 to activate the generation. After a delay tdu, the outputs 131 and 151 switch to state 0 at a time t31. The lines 13 and 15 respectively bring delays of 4 * tdu and 3 * tdu to the rising and falling edges of the signals present at the terminals 131 and 151. Consequently, the signal 133 switches to the state 1 at a time t32, posterior 3 * tdu with respect to the instant t31 and the signal 153 switches to the state 1 at a time t33, posterior of 4 * tdu with respect to the instant t31.
    The signals 131 and 151 then switch to the state 1 with a delay tdu with respect to the instants t32 and t33 respectively, and so on.
    The number of oscillations taken, preferably at the output 153 (or 133), when the oscillation stops, is random. Note that this number of oscillations can be counted at any point of the loop.
    The inventors consider that, in addition to the phase noise, one of the factors which leads to the shutdown of the generator comes in particular from an imbalance between the rise times and the signal descent times, that is to say say between the time that a delay element or a gate makes to switch from state 1 to state 0 and from state 0 to state 1. Indeed, the offset between rise times and time of descent a branch of the generator (delay line plus NAND gate) causes that there comes a time when the duration of a state becomes less than the delay provided by an element of the delay line.
    A problem is that this "moment" is a function of the number of elements delaying the line (accumulation of time offsets). However, we would like to be able to make controllable the duration at which a generator stops, so, when designing a new circuit, to be able to ensure that the number of oscillations before stopping the generator is sufficient.
    By taking again the notations of the example of FIG. 2, the following will be noted: tln, the moment of a front (rising or falling) of rank n of the signal of the output 131; t2n, the moment of an edge (rising or falling) of rank n of the signal of the output 151;
    Lln, the duration of the low level of rank n of the signal of the output 131 (this duration is related to the delay brought by the second line 17 plus the first door 13); H2n, the duration of the high level of rank n of the signal of the output 151 (this duration is related to the delay brought by the first line 11 plus the second door 15); tri and tfi, the respective rise and fall times of the signal of the output 151 with respect to the switching time of the terminal 131; and tr2 and tf2, the respective rise and fall times of the signal of the output 131 relative to the switching time of the terminal 151.
    The behavior of the generator can be written from arithmetic sequences.
    In particular, we can write:
    Lln = tl2n + 1 - tl2n; and H2n = t22n + 2 - t22n + l ·
    Furthermore, tl2n = t22n-1 + tf2 / tl2n + l = t22n + tr2 / t22n-l = tl2n-2 + sort; and t22n = tl2n-l + tfi /
    We can deduct :
    Lln = H2n-1-Afr2, with Afr2 = tf2-tr2; and H2n-1 = Lln-i + Afri, with Afri = tfi-tri. From these relationships, the recurrences of the different durations can be expressed simply as a function of the differences between rise and fall times.
    For example, for the duration Lin, we can write:
    Lln + i = Lln + Afrl - Afr2.
    Then, expressing the following from the first term
    Llo (n = 0):
    Lln = Llo "n * r, with r = Afr2 - Afri.
    We thus obtain an arithmetic sequence whose r reason is determinable, during the design of the circuit, according to the number of basic cells (delay elements) chosen and their difference between rise time and time of descent.
    A similar relation can be written for durations H2, with: H2n = H2o - n * r.
    Similarly, noting:
    Hln, the duration of the high level of rank n of the signal of the output 131 (this duration is related to the delay brought by the first line 11 plus the second door 15); L2n, the duration of the low level of rank n of the signal of the output 151 (this duration is linked to the delay brought by the first line 11 plus the second door 15); and
    The following relationships can be obtained:
    Hln = Hlo + n * r; and L2n = L2o + n * r.
    If the difference between the rise and fall times (the reason r) is negative, the times L1 and H2 increase while the durations L2 and H1 decrease. On the other hand, if the reason r is positive, the duration L1 and H2 decrease while the duration L1 and H2 increase.
    FIG. 4 represents an embodiment of an oscillation number generator taking advantage of this analysis.
    In particular, it is desired to be able to control (in order to respect characteristics desired for the random generator) the temporal behavior of the oscillation generator, that is to say the time from which it stops. This duration is not only a function of the delay caused by the delay lines but also the rise and fall times of these lines.
    Knowing the behaviors of the basic cells (delay elements) of the technology in which one wishes to realize the random generator, one can deduce the number of oscillations after which the generator will stop. With a r positive reason, we can set a limit when the duration Lln becomes zero, that is to say for n = Llo / r. In practice, the oscillations stop when the duration of the pulse becomes less than the delay of a delay element.
    According to this embodiment, each branch is composed of a delay line 21, respectively 27, said symmetrical that is to say having identical or very similar rise and fall times (difference between the rise time and of descent less than one-tenth of the reason r) in series with an element 22, respectively 28, said asymmetrical, whose rise and fall times are different from each other. An input terminal 231 the first branch is connected to the output of a first logic gate 23 of the NAND type (NAND) of which a first input 235 receives a trigger signal CTRL and a second input 233 receives the output of the second branch. An output terminal 253 of the first branch is connected to a first input of a second NAND type gate 25, a first input 255 of which receives the signal CTRL and whose output 251 is connected to the input of the second branch. The output of the generator of a random number of oscillations is for example the terminal 253 or the terminal 233. As previously, this output, therefore the counting of the oscillations, can correspond as a variant to the output 231 or 251 of the gate 23, respectively 25, or more generally at any point of the loop. In practice, the output is connected at the output of an asynchronous counter of the number of oscillations which counts the number of oscillations between the activation of the generator by the signal CTRL and the stop of the oscillations. This counter (not shown in FIG. 4) is, for example, constituted by a flip-flop or several flip-flops in cascade, the clock input of the or a first flip-flop receiving the output signal of the generator. The output or outputs of the latches provide a number on one or more bits (depending on the number of flip-flops) of which generally only the bits or the least significant bit are kept to constitute the random number.
    If necessary, several generators are used in parallel to increase the bit rate in generated random bits.
    To achieve the symmetrical delay lines 21 and 27, paired inverters, i.e., an even number of inverters in each line, are preferably used. For example, line 21 has p pairs of inverters 3 in series while line 27 has q pairs of inverters 3 in series. The numbers p and q may be the same or different from each other.
    By using pairs of inverters, not only is the signal not reversed at the output of each line, but above all, each line has an identical or very close rise and fall time (deviation less than one tenth of the reason divided by p or by q). Indeed, by using identical logic cells of the relevant technology, even if an inverter 3 made in this technology has a rise time different from its descent time, a pair of identical inverters 3 forms an element whose rise times and descent are identical. By noting tr and tf, the rise and fall times of an inverter 3, the rise and fall time of a pair becomes tr + tf (tr + tf or tf + tr depending on the direction of the input edge ). Thus, even if the times tf and tr are different from each other, their sum remains constant for all pairs of inverters. Lines 21 and 27 thus provide a determinable and constant delay regardless of the transition (rising or falling).
    Any inverter embodiment can be used (for example CMOS inverters consisting of two series transistors, NAND or NAND gateways with interconnected inputs, etc.) provided that these inverters meet the condition of associating , when they are paired in series, successively rise time and fall time, or vice versa, so that these times are summed regardless of the edge present at the input.
    To produce the asymmetrical elements 22 and 24, a non-inverting logic amplifier (buffer) element is used, with the exception of two identical inverters in series. For example, one can use an OR gate, of type AND whose two inputs are connected, or any logical function that can be reduced to an inverting function that depends only on a single input and whose ascent and descent are different. Each element 22 and 24 is chosen to have a rise time different from its descent time. In addition, the elements 22 and 24 are chosen to have different differences between rise time and fall time. Thus, we introduce the differences that will condition the shutdown of the generator. In practice, as is apparent from the formulas established above, the doors 23 and 25 also provide a shift between the rise and fall times of each branch. This offset must be added to that introduced by the element 24, respectively 22, to obtain the deviations Afri and Afr2 respectively, hence the reasons for the arithmetic sequences.
    An advantage of the proposed embodiment is that these numbers p and q of inverter pairs of lines 21 and 27 do not influence the reason for the arithmetic sequences defining the oscillations. Indeed, they condition only the first terms of each sequence, that is to say the durations of the first pulses following the switching of the CTRL signal to activate the generation.
    According to a simplified embodiment, only one element 22 or 24 is provided, the other branch having only the symmetrical delay line.
    The lines 21 and 27 may be indifferently placed upstream or downstream of the elements 22 and 24 with which they are respectively associated. Alternatively, the elements 22 and 24 are even interspersed within the lines 21 and 27, between inverters or pairs of inverters that constitute them.
    An advantage of the described embodiments is that it is now easy to size an oscillations generator and to be able to characterize it. Thus, when designing an electronic circuit comprising a random number generator, knowing the differences between the rise and fall times in the technology, it becomes easy to comply with specifications. The interpretation of the generated number is performed by counting the pulses on one of the outputs 233 and 253 and taking, as a random bit, for example, the least significant bit at the end of the counting period. The counting period is fixed by a clock signal.
    FIG. 5 represents, schematically, an alternative embodiment according to which it is sought to minimize the reason for the arithmetic sequence while keeping it easily determinable.
    According to this variant, with respect to the embodiment of FIG. 4, in parallel with each element 22, 24 or asymmetrical delay line (ADL - Asymmetry Delay Line), a second symmetrical delay line (SDL - Symmetry Delay Line) is provided. ) 26, respectively 28. The inputs of the delay lines 22 and 26 are connected at the output of the line 21. The inputs of the lines 24 and 28 are connected at the output of the line 27. The outputs of the lines 22 and 26, respectively 24 and 28, are connected to inputs of a two-to-one multiplexer 51, respectively 52, whose output is connected at the input 253, respectively 233, of the logic gate 25, respectively 23. The multiplexer 51 is controlled by a signal from a count (counter 53, CNTH) pulses of its output signal. In other words, the counter determines the number of pulses from which the asymmetrical line 22 is switched to the symmetrical line 26. On the multiplexer side 52, provision can be made for a command by the same counter 53 or by a different counter which then counts the pulses of the output of the multiplexer 52. In practice, if a single counter is used, it is placed on the branch having the longest delay so as not to switch the multiplexers before the end of the first pulses.
    Such a variant makes it possible to make the reason for the arithmetic sequences configurable, and more particularly to reduce this reason in order to delay the stopping of the generator.
    Indeed, by executing an asymmetric loop (an impulse on each branch) and the rest of the loops only with the symmetrical elements (21, 26, 27 and 28), the reason of the continuation is minimized. By repeating the notations taken above, the reason r is divided by the number of loops. This allows, among other things, to increase the number of pulses circulating in the generator delay lines while reducing the size of these delay lines.
    If necessary, the counter 53 is the counting counter of the pulses whose least significant bit or bits are used, at the end of the oscillations, to define the random number generated.
    FIG. 6 represents an embodiment of a delay line 6 that can be parameterized both as a symmetrical delay and as an asymmetrical delay.
    The embodiment of FIG. 6 may constitute, by way of a particular example in the previous embodiments, an embodiment of the symmetrical delay line, for example 21, and of the asymmetrical delay element, for example 22, of a plugged.
    According to this embodiment, one or more (in the example three) symmetrical delay lines 212, 214 and 216, that is to say each having identical rise and fall times, is associated with one or more (in example three) delay elements or asymmetrical delay lines 221, 223, 225, that is to say each having different rise and fall times, each asymmetrical or symmetrical line being short-circuitable to the using a multiplexer 61, 62, 63, 64, 65, 66 respectively. In other words, the inputs of the lines 212, 214, 216, 221, 223 and 225 are respectively connected directly to a first input of the multiplexers 61, 62, 63, 64, 65, 66 whose other input is connected to the output of the corresponding delay line. The outputs of the multiplexers 61, 62, 63, 64 and 65 are respectively connected to the inputs of the lines 214, 216, 221, 223, 225 and the output of the multiplexer 66 defines the output OUT of the parameterizable delay line.
    Each multiplexer 61 to 66 is individually controllable, for example, by a different bit, respectively [5], [4], [3], [2], [1], [0] of a word SEL_DLY.
    In an application to the production of an oscillation number generator of the type illustrated in FIG. 4, the input IN terminal of the line 6 is connected to the output (231 or 251, FIGS. 4 and 5) of the branch concerned.
    Each line 212, 214, 216 is preferably constituted by one or more pairs of inverters, that is to say of delay elements each having identical rise and fall times as described above. In the example shown, lines 212, 214 and 216 respectively comprise 32, 16 and 8 pairs of inverters, ie 32, 16 and 8 unitary symmetrical delay elements (sdelt).
    Asymmetrical lines 221, 223, 225 provide identical or different delays from each other. Preferably, the lines 221, 223 and 225 consist of identical unit elements, that is to say providing the same offset between rise time and fall time. Different numbers of these unitary elements are then provided in each of the lines, which makes the system easily parameterizable with optimum granularity. In the example shown, the lines 221, 223 and 225 respectively comprise 4, 2 and 1 single asymmetric delay elements (adelt).
    Thus, the delay line 6 is configurable both late and difference between rise time and fall time. By taking the example of identical unitary elements in the lines 212, 214 and 216, and identical unitary elements in the lines 221, 223 and 225, a symmetrical delay of between 8 and 56 times the delay can be chosen. symmetrical unit element and a time difference between rising edge and falling edge between 1 and 7 times the gap provided by the asymmetrical unit element.
    The unitary elements are, for example, made as described above in connection with FIG. 4.
    The number of symmetrical and asymmetrical delay lines depends on the desired adjustment capacity. Asymmetric elements not only have different rise and fall times but also an intrinsic delay which contributes to the total delay of the delay line.
    The embodiment of FIG. 6 can serve, for example, to integrate the same generator architecture and to make this structure parameterizable, whether at design or in application.
    The embodiment of FIG. 6 can be combined with that of FIG. 5 by putting in parallel with each asymmetric line 221, 223, 225, a symmetrical line of the same delay, thus eliminating the short circuit of the line driving the upper inputs ( in the orientation of FIG. 6) of the multiplexers 64 to 66. In a variant, 3-to-1 multiplexers are used, two inputs of which receive the respective outputs of two parallel lines of the same delay, respectively symmetrical and asymmetrical, and the third of which input directly receives the output of the multiplexer of previous rank.
    In the embodiment of FIG. 6 or its variants, in order to facilitate the parameterization, it would be desirable for the multiplexers 61 to 66 to provide symmetrical delays. However, a conventional multiplexer has asymmetric operation in terms of rise time and fall time.
    Fig. 7 shows an embodiment of a multiplexer 7 having symmetrical operation, i.e., identical rise time and fall time.
    The multiplexer 7 of FIG. 7 is a two-to-one multiplexer, that is to say that it selects one of its two inputs A or B and supplies the corresponding signal at the output Z. The selection between the input A or B is effected by a control signal S.
    The multiplexer 7 comprises four elements of multiplexing or selection two to one. It can be considered that the multiplexer 7 consists of 4 unit multiplexers 72, 74, 76 and 78 associated in chain. Multiplexers are reversing multiplexers. A first multiplexer 72 has its input terminals respectively connected to the inputs A and B. A second multiplexer 74 has its two inputs connected together to the output of the first multiplexer 72. A third multiplexer 76 has its two inputs connected together at the output of the second multiplexer 72. second multiplexer 74. A fourth multiplexer 78 has its two inputs connected together to the output of the third multiplexer 76 and its output provides the output Z. The signal S directly controls the multiplexers 72 and 74 and, after passing through an inverter 75, the multiplexers 76 and 78.
    The fact that the multiplexers 74, 76 and 78 have their interconnected inputs results in that they in fact make no selection. However, assuming all the multiplexers 72, 74, 76 and 78 are identical, they all have identical rise and fall times. In addition, they all behave similarly at a front on their first entry and all behave similarly at a front on their second entry.
    Noting tr the rise times, tf the descent times and assigning these notations a first index A, respectively B, depending on whether the front is on the input A (the first input of the unit multiplexer concerned) or B ( the second input of the unit multiplexer concerned) and a second index 72, 74, 76 or 78 depending on the unitary multiplexer concerned, it is possible to write: trA72 = trA74 = trA76 = trA78 = trA; tfA72 = tfA74 = tfA76 = tfA78 = tfA; trR72 = trB74 = trB76 = trs78 = trB; and tfB72 = tfB74 = tfB76 = tfB78 = tfB.
    Due to the inversion of the control of the two multiplexers 76 and 78 with respect to that of the multiplexers 72 and 74, the rise and fall times of the multiplexer 7, from the input A or B to the output Z, can be written, depending on whether a rising edge r or a falling edge f is present on the input A or on the input B: trAz = tfA72 + trA74 + tfR76 + trB78; tfAz = trA72 + tfA74 + trB76 + tfB78 / trBz = tfB72 + trB74 + tfA76 + trA78; and tfBz = trB72 + tfB74 + trA76 + tfA78.
    Since the unit rise and fall times are identical for a given input, we deduce: trAz = tfAz = trBz = tfBz = trA + tfA + trB + tfB.
    Therefore, the rise and fall times of the multiplexer 7 are identical regardless of the input considered. The multiplexer is therefore symmetrical with the definition given above.
    Alternatively, provision may be made to invert the control at other locations provided that two multiplexers select their respective first inputs when the other two select their respective second inputs. In this case, however, it will be ensured that the propagation delay provided by the inverters is not greater than the minimum propagation time of a unitary multiplexer, otherwise the output is distorted. An advantage of the embodiment of Figure 7 is that it ensures that the selection of the multiplexers 76 and 78 is active before the signal (the front) has finished passing through the multiplexers 72 and 74.
    Although this does not provide any advantage in terms of symmetry, it is possible to use 8, 12, 16 and more generally any multiple of four of unitary multiplexers provided that the half is controlled in inverse relation to the other half. This allows, for example, to increase the propagation time without impairing the symmetry of operation.
    An advantage of the embodiment of FIG. 7 is that it is independent of the internal structure of the unitary multiplexers. Indeed, provided that identical unitary multiplexers are used, the described operation is respected.
    A multiplexer as shown in FIG. 7 has multiple applications. In particular, it is common that it is advantageous to have a symmetrical operation. As a particular example of application, the multiplexer of FIG. 7 can be used to make each of the multiplexers 61, 62, 63, 64, 65 and 66 of the embodiment of FIG. 6. An advantage is then that the reason number generator pulse sequences remain uniquely related to asymmetric elements 221, 223 and 225, which facilitates sizing.
    The structure of the multiplexer 7 of FIG. 7 can be adapted to make multiplexers with more than two inputs.
    Figure 8 shows an embodiment of a four-to-one symmetric multiplexer.
    According to this embodiment, three two to one multiplexers of the type of that of FIG. 7 are used. A first multiplexer 7a defines two inputs A and B. A second multiplexer 7b defines inputs C and D. The respective outputs of the multiplexers 7a and 7b are connected to the two inputs of a third multiplexer 7c whose output defines the output Z 'of the multiplexer four to one. The multiplexers 7a and 7b are respectively controlled by a signal SI and by its inverse. The multiplexer 7c is controlled by a signal S2. For example, assuming a two-bit selection word, the signal S2 is constituted by the most significant bit and the signal S1 by the least significant bit.
    In a random number generator of the type described above, the interpretation of the output of the generator requires counting the pulses present at the output. It is this count that determines the fired number. For example, as the random bit generated by the generator 20, the low-order bit of the count of the pulses present at the output of the generator between its release and a counter reading signal after the oscillation stops is taken. The time interval between the triggering of the generator and the read signal is chosen according to the range of possible time intervals conditioned by the sizing of the delay lines of the generator.
    However, in a counter, there may be an imbalance between the state 1 and state 0 accounts in particular if one of the states of the signal to be counted becomes too short relative to the other. This phenomenon is due to the fact that after a certain pulse duration (in the decreasing direction of duration), the counter is only able to take the pulse into account in one direction according to the parity of the current account. that it contains. We then find ourselves with an imbalance between the probability of drawing a 1 and drawing a 0. In other dull, with a generator of the type of that of Figure 4 (but also with that of Figure 2), when the cyclic ratio becomes too deformed, the use of the output of the generator as counting clock leads to the duration of the pulse (low or high depending on the output concerned) is less than the minimum time of taking into account the flip-flop. But this time differs for a high state and a low state. Therefore, whatever the output used, the flip-flop will come out of its normal operation and it can not be determined in advance, when designing, which output will be concerned.
    This problem is likely to be encountered not only for counting the number of oscillations in a generator as described in the present description but more generally for counting events of short duration in a signal, for example a transient disturbance detector (glitch). .
    Indeed, a counter, whether asynchronous or not, normally operates with a so-called square clock, that is to say with a duty cycle close to 50%. However, in the case of the generator described above, the duty cycle of the clock of the asynchronous counter, which corresponds to the output 231 or 251 (or 233, 253), decreases with each period until the stop of the oscillation, or on the contrary increases with each period until the stop of the oscillation. Therefore, one of the outputs stops at state 0 and the other one stops at state 1. However, it is generally not known with certainty in advance which outputs will stop in the state 1 and which will stop in state 0. On the counter side, we use latches which require in their specifications, a minimum duration of the clock in the high state (1) and a minimum duration of the clock signal in the low state (0), for example arbitrarily 110 ps for the minimum duration in the high state and 87 ps for the minimum duration in the low state. Therefore, when the counter input latch receives a very low or very large duty cycle clock, it may eventually run out of specification and the clock signal pulse is not taken into account.
    FIG. 9 represents an embodiment of a random number generator of the type described above with its pulse counting elements making it possible to format the generated number.
    FIG. 9 illustrates a variant in which the numbers of pulses generated are taken at the output of gates 231 and 251.
    According to this embodiment, each output 251, 231 of the random oscillation number generator 20 (RONG), for example as described in FIG. 4, is connected to the input of a counter, respectively 91 (CNTR), 93 ( CNTL). Each counter 91, 93 counts the pulses of the corresponding output signal of the generator. Each counter is an asynchronous counter, for example of flip-flop type D.
    The reading of the counters 91 and 93 is triggered by a READ signal which transfers the accounts to a decision circuit 95 (DECIS) or combination. The circuit 95 also receives the output signals 231 and 251 in order to know, during the decision, the states of these signals at the stop of the oscillations.
    Functionally, we use counters of the number of oscillations, one with an output of the generator 20, the other with the other output of the generator 20. As indicated above, one of the counters will stop working before the other, that is to say that its input latch will stop working before the input latch of the other, under the effect that the minimum operating times of the latches are different for the low state and for the high state. In fact, one of the counters will stop under the effect of an oscillation not respecting its minimum time in the low state while the other counter will stop under the effect of an oscillation not respecting his time minimum in the high state.
    Depending on the applications, the choice criterion, by the circuit 95 between the outputs of the counters 91 and 93 according to the states provided by the outputs 231 and 251, differs. This selection criterion can be conditioned by a simulation of the operation of the generator to determine if the flip-flops stop because of the minimum time in the high state or because of the minimum time in the low state.
    For example, if one attaches importance to the parity of the counting result and assuming that the latch of the counter which stops the first one stops under the effect of a duration of low time (state 0 ) too low, the value of the corresponding counter will be lower than the value of the other counter. If this effect is cumulative with an asymmetric operation of the flip-flop, that is to say an easier switchover from 0 to 1 than from 1 to 0 (or vice versa), this introduces a bias in the generation of the random number that is not desirable. We then select the counters that stopped on a switch from 1 to 0.
    According to yet another example where parity is less important than a high number of oscillations, the counter which stops last is selected.
    According to yet another example, the decision depends on the relationship between the meters. Thus, we keep the value: of the counter having the greatest account if the two accounts have the same parity; or the counter with the largest account if this account is even and the smallest if the account is odd.
    In yet another example, it is considered that the counters that continues to operate has a high risk of operating asymmetrically because the other meter has already stopped. In this case, the block 95 selects the result of the counter which stops first, that is to say the first which, during a change of state of the output 231 or 251, does not change its bit of low weight. This exemplary embodiment is preferred in the case where it has not been determined, in simulation, the cause of stopping flip-flops (minimum time in the low state or minimum time in the high state).
    Counting the two outputs and taking one or the other as appropriate makes it possible to miss no impulse.
    It will be noted that the counting circuit described with reference to FIG. 9 applies more generally to any random number generator and not necessarily to that of FIG. 4. In particular, it may be implemented for any random number generator. having delay lines looped over each other (for example, Figure 2).
    According to another embodiment of this counting aspect, the signals provided by the outputs 253 and 233 are shaped before being counted in order to eliminate some possible misses in the count. For this, optional shaping circuits (SHAPER) 97 are interposed between the respective outputs 251 and 231 and the counters 91 and 93.
    Figure 10 shows an embodiment of a shaping circuit 97 of a pulse signal.
    The circuit 97 comprises a D-type flip-flop 972 whose input D is forced to the high state (1) and whose non-inverted output Q defines the output S97 supplying the shaped signal. The clock input CK of the flip-flop 972 defines the input of the circuit receiving the pulse signal to be shaped. The inverted output NQ of the flip-flop 972 is connected via a non-inverter delay element 974 (DELAY) to a first input of an AND-type logic gate 976, an output of which is connected to the reset input. RN (active on rising edge) of the flip-flop 972. A second input of the gate 976 is intended to receive an RSTN activation signal of the circuit 97. When the signal RSTN is in the 0 state, the circuit 97 is not active and the output S97 is permanently in state 0. The gate 976 is therefore optional if one does not need to disable the circuit 97.
    The value of the delay introduced by element 974 is chosen to be greater than the minimum pulse width that can be captured by flip-flop D.
    FIGS. 11A, 11B, 11C and 11D illustrate, in the form of timing diagrams, the operation of the shaping circuit of FIG. 10. FIG. 11A shows an example of the shape of the input signal CK to be shaped. Fig. 11B shows an example of a corresponding pace of the Q output signal (S97). Fig. 11C shows an example of a corresponding pattern of the output NQ. Fig. 11D shows an example of a corresponding pace of the signal of the RN input.
    A positive pulse signal CK is assumed.
    Initially, the output Q (thus the output S97) is in the state 0, the output NQ is in the state 1. The input RN is in the state 1. We assume the active signal RSTN (state 1). At the appearance (time t90) of a rising edge on the clock signal CK, as the input D is in the state 1 and the input RN is in the state 1, this pulse is transmitted on the output Q which switches to state 1. On the other hand, the output NQ (inverse of the output Q) switches to the state 0. This state is transmitted, with a delay DELAY on the input RN (considering the delay brought by the gate 976 included in the value DELAY). Switching the RN input to the DELAY delay end causes the Q output to be set to 0 and, consequently, the NQ output to 1, which in turn causes the After the delay DELAY, the switching of the input RN to the state 0. The flip-flop is then ready to take a new state into account. The right part of the timing diagrams illustrates the operation with a pulse CK of duration less than the delay DELAY. The delay DELAY sets the duration of the pulses of the output signal independently of the duration of the signal pulse CK. Therefore, even if the signal pulse CK is theoretically too short for its descent to be taken into account, it is still present on the Q output.
    The duration DELAY sets the duration of the pulses of the signal S97, therefore the input of the counters in the embodiment of FIG.
    To realize a shaping circuit operating with a pulse signal of negative pulses, the output of the gate 976 is connected to the set input of the flip-flop, the input is forced to state 0 and the the delay element receives the non-inverted output Q while the output of the shaping circuit is defined by the inverted output NQ. The operation is transposed without difficulty from the explanations given above.
    An advantage of the embodiments that have been described is that they make it possible to design or configure a random number generator in a reliable and determinable manner. Thus, we can meet the criteria set by specifications and validate that the generator meets these specifications.
    Another advantage is that the solution described is compatible with the use of standard cells of a given technology.
    Another advantage is that the entire generator is achievable with logic elements.
    For a random number generator, the number is taken either after a fixed time interval, triggered by the activation of the generator (signal CTRL) and chosen to be greater than the maximum stop time of the generator, or by detecting the stopping the meter (s).
    To realize a non-clonable number generator of the identifier type of an integrated circuit, the delay lines and the reason for the arithmetic sequences are sized to set the number of oscillations. The sampling of the number is carried out after the shutdown of the generator as for a random number generator and preferably only a part of the (most significant) bits are retained.
    Various embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, the choice of the delays brought by the symmetrical delay lines and the shifts provided by the asymmetrical delay elements depends on the application and the specifications of the generator. Finally, the practical implementation of the embodiments that have been described is within the abilities of those skilled in the art from the functional indications given above.
    权利要求:
    Claims (7)
    [1" id="c-fr-0001]
    1. Logic multiplexer (7), two to one, comprising: two input terminals (A, B); an output terminal (Z); a wedge terminal (S); and a plurality of four one-to-one unit multiplexers (72, 74, 76, 78) connected in series, a first unitary multiplexer (72) having its inputs connected to the input terminals, a last unitary multiplexer (78) having its output connected to the output terminal and the other unitary multiplexers (74, 76) having their respective inputs interconnected to the output of the preceding multiplexer in the series association, one-half of the unit multiplexers being reverse-controlled (75) with respect to a other half.
    [2" id="c-fr-0002]
    The multiplexer of claim 1, wherein the unitary multiplexers (72, 74, 76, 78) are reversing multiplexers.
    [3" id="c-fr-0003]
    The multiplexer according to claim 1 or 2, wherein all unit multiplexers (72, 74, 76, 78) are identical.
    [4" id="c-fr-0004]
    The multiplexer according to any one of claims 1 to 3, wherein one half of the multiplexers has its control inputs connected to said control terminal (S).
    [5" id="c-fr-0005]
    The multiplexer according to claim 4, wherein the other half of the multiplexers has its kernel inputs connected to the output of a multiplexer (75) having an input connected to said control terminal (S).
    [6" id="c-fr-0006]
    6. Four-to-one multiplexer (8), comprising three two-to-one multiplexers (7) according to any one of claims 1 to 5, the inputs of two two-to-one multiplexers defining the inputs of the four-to-one multiplexer and the respective outputs. of these two multiplexers being connected to the two inputs of a third multiplexer whose output defines the output of the multiplexer four to one.
    [7" id="c-fr-0007]
    7. Number generating circuit comprising at least one multiplexer (7, 8) according to any one of claims 1 to 6.
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    同族专利:
    公开号 | 公开日
    CN206977395U|2018-02-06|
    FR3051085B1|2020-02-14|
    US10103721B2|2018-10-16|
    US20170324405A1|2017-11-09|
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    2017-11-10| PLSC| Publication of the preliminary search report|Effective date: 20171110 |
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1654080|2016-05-04|
    FR1654080A|FR3051085B1|2016-05-04|2016-05-04|MULTIPLEXER STRUCTURE|FR1654080A| FR3051085B1|2016-05-04|2016-05-04|MULTIPLEXER STRUCTURE|
    EP16198958.7A| EP3242397A1|2016-05-04|2016-11-15|Multiplexer structure|
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    CN201611083404.7A| CN107346400B|2016-05-04|2016-11-30|Multiplexer structure|
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